1. Field of the Invention
The invention relates to a method for tracking a clock, and more particularly, to a method for tracking a delay locked loop (DLL) clock.
2. Description of Related Art
A delay lock loop (DLL) processes a reference clock signal to generate a sequence of delayed clock signals. The frequency and period of the reference clock signal are the same as those of each of the generated clock signals except each delayed clock signal is phase shifted by a common delay time from the previous delayed clock signal. When operating properly, the DLL provides delay clock signals with positive edge transitions that span a single period of the reference clock signal. Initially, the delay time of each of delay cells may be set to a fixed delay time whatever the reference clock signal is. Over time, the fixed delay time results in a sequence of delayed clock signals that may or may not span a single period of the reference clock signal. When the DLL converges on an improper delay time, it is falsely locked. In general, once the reference clock signal is slow down, more delay cells will be used to lock the reference clock signal and hence results in more power consumption.